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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ANALOG VOLTAGE SUPPLY (VPWR)
The VPWR pin is battery input to the 33811 IC. The VPWR
pin requires external reverse battery and transient protection.
Maximum input voltage on VPWR is 15.5V for full operation.
All IC analog current is provided from the VPWR pin through
an internal voltage regulator. The VPWR pin requires
adequate decoupling capacitance to the A_GND pin.
DIGITAL VOLTAGE SUPPLY (VDD)
The VDD pin is Logic Supply input to the 33811 IC. Maximum
input voltage on VDD is 5.25V for full operation. All IC digital
logic current except the SPI SO output pin is provided from
the VDD pin. The VDD pin requires adequate decoupling
capacitance to the D_GND pin.
SPI INTERFACE VOLTAGE (VSPI)
The VSPI input pin is used to determine communication logic
voltage levels between the microprocessor and the 33811
device. Current from VSPI is used to drive SO output and
pull-up current for CS and SI. VSPI must be connected to +5
Volts or +3.3 Volts for normal operation.
a logic low state, command words may be sent to the 33811
via the serial input (SI) pin, and status information is received
by the MCU via the serial output (SO) pin. The falling edge of
CS enables the SO output and transfers status information
into the SO buffer.
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high-impedance)
2. Activates the received command word, allowing the
33811 to activate/deactivate output drivers.
To avoid any spurious data, it is essential the high-to-low
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. Internal to the 33811 device is an
active pull-up to V SPI on CS. In cases where voltage exists on
CS without the application of V SPI , no current will flow from
CS to the V SPI pin.
SERIAL INPUT DATA (SI)
The SI pin is used for serial instruction data input. SI
information is latched into the input register on the rising edge
of SCLK. A logic high state present on SI will program a one
in the command word on the rising edge of the CS signal. To
program a complete word, 16 bits of information must be
entered into the device.
ANALOG GROUND (A_GND)
The Analog Ground (A_GND) pin provides a low current
analog ground for the IC. The VPWR supply is referenced to
the A_GND pin. The A_GND pin should be used for
decoupling the VPWR pin.
DIGITAL GROUND (D_GND)
The Digital Ground (D_GND) pin provides a dedicated
ground for the VDD and VSPI supplies and should be
connected to the A_GND pin.
SERIAL CLOCK INPUT (SCLK)
The system clock (SCLK) pin clocks the internal shift
register of the 33811. The SI data is latched into the input
shift register on the rising edge of SCLK signal. The SO pin
shifts status bits out on the falling edge of SCLK. The SO data
is available for the MCU to read on the rising edge of SCLK.
With CS in a logic high state, signals on the SCLK and SI pins
will be ignored and the SO pin is tri-state.
SERIAL OUTPUT DATA (SO)
The SO pin is the output from the shift register. The SO pin
remains tri-stated until the CS pin transitions to a logic low
state. All normal operating drivers are reported as zero, all
faulted drivers are reported as one. The negative transition of
CS enables the SO driver.
The SI / SO shifting of the data follows a first-in-first-out
protocol, with both input and output words transferring the
most significant bit (MSB) first.
RESET INPUT (RESET)
The RESET pin is an active high digital input pin used to
clear the fault outputs and registers in the device. During
normal operation the RESET pin should be held low.
SOLENOID MONITOR INPUT (SOLM1, SOLM2,
SOLM3, SOLM4, SOLM5)
These are the five solenoid monitor inputs that are
connected to the Solenoid solenoid driver output pins.
CHIP SELECT (CS)
The system MCU selects the 33811 to receive
communication using the chip select (CS) pin. With the CS in
33811
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
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